G2992BT11U

2A DDR Bus Termination Regulator
The G2992B is a linear regulator designed to meet the JEDEC SSTL-18, SSTL-2 and SSTL-3 (Series Stub Termination Logic) specifications for termination of DDR I/ II/ III -SDRAM. It contains a high-speed operational amplifier that provides excellent response to the load transients. This device can deliver 2A continuous current in the application such as required for DDR I/ II/ III SDRAM termination. The G2992B can easily provide the accurate VTT voltage with two external resistors generating reference voltage. The quiescent current is as low as 750µA @ VCNTL = 3.3V. So the power consumption can meet the low power consumption applications. The G2992B also has a shutdown function by setting VREF smaller than 0.2V, that provides Suspend to RAM (STR) functionality. When in the shutdown mode, the VTT output (on VOUT pin) will be tri-state providing a high impendence. A power saving advantage can be obtained in this mode through lowering the quiescent current to 50μA @ VCNTL = 3.3V.

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Specifications
VDDQ (V)
min.
1.2
max.
3.6
Isource
(A)
2
Isink
(A)
2
IVREF
(mA)
--
VCNTL
(V)
3~5.5
EN
NO
Note
DDR1/2/3
Package
SOT-23-5
Datasheet
EDS-2992B-464-130507-0.8.pdf
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