G2995F1Uf
DDR Termination Regulator
The G2995 is a linear regulator designed to meet the JEDEC SSTL-2 and SSTL-3 (Series Stub Termination Logic) specifications for termination of DDR-SDRAM. It contains a high-speed operational amplifier that provides excellent response to the load transients. This device can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. With an independent VSENSE pin, the G2995 can provide superior load regulation. The G2995 provides a VREF output as the reference for the applications of the chipset and DIMMs.
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Specifications
|
VDDQ (V)
|
min.
|
1.6 |
|---|---|---|
|
max.
|
5.5 | |
|
Isource
|
(A)
|
1.5 |
|
Isink
|
(A)
|
1.5 |
|
IVREF
|
(mA)
|
0.03 |
|
VCNTL
|
(V)
|
1.8~5.5 |
|
EN
|
NO | |
|
Note
|
DDR1/2 | |
|
Package
|
SOP-8(FD) | |
|
Datasheet
|
EDS-2995-118-2.0-090414.pdf | |
